1 Pattern-Aware Dynamic Thread Mapping Mechanisms for Asymmetric Manycore Architectures

Recent factors in the architecture community such as the power wall and on-chip complexity have caused a shift to manycore architectures and multi-threaded workloads. An emerging architecture for general purpose processing is an asymmetric chip layout composed of cores with varying levels of complexity and power. This work considers thread behavior that results from parallel programs and proposes four new thread mapping schemes for this asymmetric architecture. These schemes leverage the behavior of common programming patterns used in parallel programming to target typical thread behavior. The patterns targeted include the pipeline parallelism, divide and conquer, and recursive data patterns. The proposed predictors out-perform base asymmetry aware schemes by at most 40 % and existing dynamic schemes by as much as 23 % for the PARSEC and SSCA2 benchmarks. Additionally, this work demonstrates the relationship between thread heterogeneity and the parallel pattern used to create the workload, thus creating a link between programmer and architect that can be leveraged to create more intelligent thread mapping schemes. 1