Education

{ Domain-specific language for HLS – The aim of this project is to enable accessibility of FPGA designs for non-hardware experts by using architecture-oriented domain-specific language based HLS templates (DSL-HLS templates). DSL-HLS template (embedded in host programming language) define parameterizable efficient hardware architectures for common kernels in different domains. { Pattern Oriented High-Level Synthesis – The aim of this project is to make FPGA designs easier by exploiting commonly occurring design patterns in a wide range of applications. { Software Defined Radio – The aim is to design SDR wireless channel emulator on an FPGA platform. { Face Detection on an FPGA – The aim of this project is to design a low power high performance FPGA face detection system. { Face Recognition on an FPGA – An FPGA based face recognition system. The aim of this project implementing existing face recognition algorithm and producing a complete face recognition system. The complete system is a system which has a camera interfaced with FPGA, the system scans each frame and detects face(s) in a frame and recognizes each detected face. { Simulate & Eliminate – A Top-to-Bottom Design Methodology for Application-Specific Multi-Core Architec-tures: This project aims to create a tool, called Simulate & Eliminate (S&E), which generates completel