The Terascale Computing System (TCS) is a new high-performance machine that was recently installed by researchers at the Pittsburgh Supercomputing Center (PSC). The TCS was constructed using commod-ity hardware components that communicate over a high-speed Quadrics Elan intercon-nection network. The PSC is also build-ing a visualization subsystem for the TCS using a cluster of high-end workstations equipped with nVidia-based graphics accel-erators and Quadrics Elan interconnection hardware. Unfortunately, Quadrics does not provide a high-level programming interface to access the low-level abilities provided by the Elan hardware. In addition, neither WireGL nor Chromium, the software packages being used for graphics rendering, support the El...
Recent research has shown that scalable, high-performance graph-ics systems may be built from commod...
This paper describes two prototype implementations of the Cube-4 architecture on the Teramac hardwar...
In this chapter we describe the architecture of a torus interconnect and its implementation on FPGAs...
To make whole one image on screens that is generated by many computers and synchronization among com...
In computer graphics, rendering is the process by which an abstract description of a scene is conver...
The recent availability of high-performance, low-cost commodity graphics hardware has brought about ...
As numerous implementations have demonstrated, software-based parallel rendering is an effective way...
Journal ArticleUsing parallel computers for computer graphics rendering dates back to the late 1970...
This paper will present the initial findings of a research into distributed computer rendering. The ...
This article provides background information about interconnection networks, an analysis of previous...
There continue to be a proliferation of simulation/animation software packages. These packages typi...
Abstract—LambdaGrid applications as typified by data-intensive collaborative visualization are likel...
In computer graphics, rendering is described as the process of converting a description of a scene t...
This diploma shows how to solve a compute-intensive problem using a graphics processing unit. Curre...
In this paper, a rendering system is presented, which utilizes efficient parallel methods for solvin...
Recent research has shown that scalable, high-performance graph-ics systems may be built from commod...
This paper describes two prototype implementations of the Cube-4 architecture on the Teramac hardwar...
In this chapter we describe the architecture of a torus interconnect and its implementation on FPGAs...
To make whole one image on screens that is generated by many computers and synchronization among com...
In computer graphics, rendering is the process by which an abstract description of a scene is conver...
The recent availability of high-performance, low-cost commodity graphics hardware has brought about ...
As numerous implementations have demonstrated, software-based parallel rendering is an effective way...
Journal ArticleUsing parallel computers for computer graphics rendering dates back to the late 1970...
This paper will present the initial findings of a research into distributed computer rendering. The ...
This article provides background information about interconnection networks, an analysis of previous...
There continue to be a proliferation of simulation/animation software packages. These packages typi...
Abstract—LambdaGrid applications as typified by data-intensive collaborative visualization are likel...
In computer graphics, rendering is described as the process of converting a description of a scene t...
This diploma shows how to solve a compute-intensive problem using a graphics processing unit. Curre...
In this paper, a rendering system is presented, which utilizes efficient parallel methods for solvin...
Recent research has shown that scalable, high-performance graph-ics systems may be built from commod...
This paper describes two prototype implementations of the Cube-4 architecture on the Teramac hardwar...
In this chapter we describe the architecture of a torus interconnect and its implementation on FPGAs...