Design space exploration for efficient data intensive computing on socs

Abstract Finding efficient implementations of data intensive applications, such as radar/sonar signal and image processing, on a system-on-chip is a very challeng-ing problem due to increasing complexity and performance requirements of such applications. One major issue is the optimization of data transfer and storage micro-architecture, which is crucial in this context. In this chapter, we propose a compre-hensive method to explore the mapping of high-level representations of applications into a customizable hardware accelerator. The high-level representation is given in a language named Array-OL. The customizable architecture uses FIFO queues and a double buffering mechanism to mask the latency of data transfers and external mem-ory access. The mapping of a high-level representation onto a given architecture is achieved by applying loop transformations in Array-OL. A method based on integer partition is used to reduce the space of explored solutions. Our proposition aims at facilitating the inference of adequate hardware realizations for data intensive appli-cations. It is illustrated on a case study consisting in implementing a hydrophone monitoring application.