Power grid design and analysis is a critical part of modern VLSI chip design and demands tools for accurate modeling and efficient analysis. In this thesis, we develop new solutions for solving power grids, both incrementally and in total, based on an approach that uses random walks. The process of power grid design is inherently iterative, during which numerous small changes are made to an initial design, either to enhance the design or to fix design constraint violations. Due to the large sizes of power grids in modern chips, updating the solution for these perturbations can be a computationally intensive task. The first issue addressed in the thesis relates to the problem of incremental analysis of power grids. We introduce two increment...
Abstract — Modern sub-micron VLSI designs include huge power grids that are required to distribute l...
Due to recent aggressive process scaling into the nanometer regime, power delivery network design fa...
Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to sheer network com...
University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: S...
It is found that the efficiency of the generic random walk analyzer varies for power grids with diff...
This paper presents a linear-time algorithm for the DC analysis of a power grid, based on a random w...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.We propose a novel approach t...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2019.Wi...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
In this paper, we present a novel stochastic simulation approach based on extended Krylov subspace m...
Power has become an important design closure parameter in today’s ultra low submicron digital design...
The purpose of this thesis is to expand the rigor of the development of new power flow solvers throu...
The design and analysis of the power distribution and supply system on a chip is a complex issue. Th...
In this paper, we investigate the impact of interconnect and de-vice process variations on voltage f...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
Abstract — Modern sub-micron VLSI designs include huge power grids that are required to distribute l...
Due to recent aggressive process scaling into the nanometer regime, power delivery network design fa...
Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to sheer network com...
University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: S...
It is found that the efficiency of the generic random walk analyzer varies for power grids with diff...
This paper presents a linear-time algorithm for the DC analysis of a power grid, based on a random w...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.We propose a novel approach t...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2019.Wi...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
In this paper, we present a novel stochastic simulation approach based on extended Krylov subspace m...
Power has become an important design closure parameter in today’s ultra low submicron digital design...
The purpose of this thesis is to expand the rigor of the development of new power flow solvers throu...
The design and analysis of the power distribution and supply system on a chip is a complex issue. Th...
In this paper, we investigate the impact of interconnect and de-vice process variations on voltage f...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
Abstract — Modern sub-micron VLSI designs include huge power grids that are required to distribute l...
Due to recent aggressive process scaling into the nanometer regime, power delivery network design fa...
Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to sheer network com...