In order to adequately account for nanometer effects during tim-ing analysis, archaic standard cell models must be replaced. Sim-plifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the character-ization process because the typical voltage waveform used during characterization does not contain a noise component. This paper introduces two new technologies for standard cell and interconnect timing analysis: Blade and Razor. Blade is a novel cell model and runtime engine based on current flow. Razor is the accompanying interconnect model. Both Blade and Razor produce and consume arbitrary voltage waveforms with nea...
With the continued scaling of chip manufacturing technologies, the significance of process variation...
This paper describes the design of new method of propagation delay measurement in micro and nanostru...
Current source model has become a good concern in logic cells. These standard cells must be presente...
(STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay ...
A simplified method for characterization of standard library cells based on the linear delay model i...
This paper describes a novel technique to analyze the effects of supply voltage noise on circuit del...
The following work shows an innovative approach to model the timing of standard cells. By using math...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Abstract—As manufacturing processes continue to shrink and supply voltages drop, timing margins due ...
In Deep Sub-Micron technologies post-layout timing analysis has become the most critical phase in th...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
Restricted until 13 Dec. 2009.This dissertation investigates the effect of capacitive crosstalk on t...
In nanoscale digital CMOS IC design, the large technology parameter variations have boosted the inte...
Abstract—Logic Cell modeling is an important component in the analysis and design of CMOS integrated...
With the continued scaling of chip manufacturing technologies, the significance of process variation...
This paper describes the design of new method of propagation delay measurement in micro and nanostru...
Current source model has become a good concern in logic cells. These standard cells must be presente...
(STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay ...
A simplified method for characterization of standard library cells based on the linear delay model i...
This paper describes a novel technique to analyze the effects of supply voltage noise on circuit del...
The following work shows an innovative approach to model the timing of standard cells. By using math...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Abstract—As manufacturing processes continue to shrink and supply voltages drop, timing margins due ...
In Deep Sub-Micron technologies post-layout timing analysis has become the most critical phase in th...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
Restricted until 13 Dec. 2009.This dissertation investigates the effect of capacitive crosstalk on t...
In nanoscale digital CMOS IC design, the large technology parameter variations have boosted the inte...
Abstract—Logic Cell modeling is an important component in the analysis and design of CMOS integrated...
With the continued scaling of chip manufacturing technologies, the significance of process variation...
This paper describes the design of new method of propagation delay measurement in micro and nanostru...
Current source model has become a good concern in logic cells. These standard cells must be presente...