Effective management of DRAM bandwidth in multicore processors

Technology trends are leading to increasing number of cores on chip. All these cores inherently share the DRAM bandwidth. The on-chip cache resources are limited and in many situa-tions, cannot hold the working set of the threads running on all these cores. This situation makes DRAM bandwidth a crit-ical shared resource. Existing DRAM bandwidth management schemes provide support for enforcing bandwidth shares but have problems like starvation, complexity, and unpredictable DRAM access latency. In this paper, we propose a DRAM bandwidth management scheme with two key features. First, the scheme avoids unex-pected long latencies or starvation of memory requests. It also allows OS to select the right combination of performance and strength of bandwidth share enforcement. Second, it provides a feedback-driven policy that adaptively tunes the bandwidth shares to achieve desired average latencies for memory ac-cesses. This feature is useful under high contention and can be used to provide performance level support for critical ap-plications or to support service level agreements for enterprise computing data centers. 1