Reconfigurable ALU Array Architecture with Conditional Execution

Abstract — Recent technology development enables differ-entiation not only in application specific cores but also in reconfigurable architectures, leading to a plethora of different reconfigurable architectures under research and development. This paper considers applying predicated execution—a well known technique to transform control dependency into data dependency for instruction level parallel processors—to a class of reconfigurable architectures, namely Reconfigurable ALU Array (RAA) architectures. Traditionally in a system consisting of a RISC processor and a RAA coprocessor, control flow operations are performed in the RISC processor and only the data-parallel part of an algorithm is performed in the RAA coprocessor. By extending the capability of RAA architectures to support in-loop conditionals, we can expect better performance in algorithm partitioning and implemen-tation. In this paper we present our architecture extensions to support predicated execution on RAAs. We also present our evaluation results comparing the architecture extensions in terms of performance as well as implementation overhead such as area and speed