Add to ORKGThe distribution of a synchronous clock in System-on-Chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the Globally Asynchronous, Locally Synchronous try to solve this issue by partitioning the SoC into isolated synchronous islands. This paper describes the bi-synchronous FIFO used on the DSPIN Network-on-Chip capable to interface systems working with different clock signals (frequency and/or phase). Its interfaces are synchronous and its architecture is scalable and synthesizable in synchronous standard cells. The metastability situations and its latency are analyzed. Its throughput, maximum frequency, and area are evaluated in function of the FIFO depth. 1
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design ...
With increasing integration densities, large chip designs are commonly partitioned into multiple clo...
As advances in VLSI technology enable higher levels of integration in system-on-a-chip (SoC) designs...
Customization of IP blocks in a multi-processor system-on-chip (MPSoC) is the historical approach to...
Abstract. This paper presents three high-throughput low-latency FIFOs that can be used as efficient ...
CMOS scaling has resulted in miniaturized high speed and high density system on a chip (SoC) designs...
Low latency asynchronous first-in-first-out (FIFO) in dual-supply systems is presented in this paper...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
The distribution of a single global clock across a chip has become the major design bottleneck for h...
this paper presents two asynchronous links between any two independently clocked synchronous modules...
A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which i...
With an ever-decreasing minimum feature size, integrated circuits have more transistors, run faster...
This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integ...
Abstract — Interconnect delays are increasingly becoming the dominant source of performance degradat...
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design ...
With increasing integration densities, large chip designs are commonly partitioned into multiple clo...
As advances in VLSI technology enable higher levels of integration in system-on-a-chip (SoC) designs...
Customization of IP blocks in a multi-processor system-on-chip (MPSoC) is the historical approach to...
Abstract. This paper presents three high-throughput low-latency FIFOs that can be used as efficient ...
CMOS scaling has resulted in miniaturized high speed and high density system on a chip (SoC) designs...
Low latency asynchronous first-in-first-out (FIFO) in dual-supply systems is presented in this paper...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
The distribution of a single global clock across a chip has become the major design bottleneck for h...
this paper presents two asynchronous links between any two independently clocked synchronous modules...
A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which i...
With an ever-decreasing minimum feature size, integrated circuits have more transistors, run faster...
This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integ...
Abstract — Interconnect delays are increasingly becoming the dominant source of performance degradat...
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design ...
With increasing integration densities, large chip designs are commonly partitioned into multiple clo...
As advances in VLSI technology enable higher levels of integration in system-on-a-chip (SoC) designs...