An FIR-Embedded Noise Filtering Method for Fractional-N PLL Clock Generators

Abstract—This paper describes a noise filtering method for fractional- PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and com-plicates filtering out high-frequency quantization noise from the modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz frac-tional- PLL is implemented in 0.18 m CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30 % reduction in short-term jitter