ArChIVED: High Performance Validation of Microprocessors Using Event Digests

Simulation-based techniques play a key role in validating the func-tional correctness of microprocessor designs. A common approach for microprocessors (called instruction-by-instruction, or IBI check-ing) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each in-struction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI check-ing methodology. Indeed, validation on these platforms require logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach fol-lowing this paradigm entails a large slowdown of the acceleration platform, because of the sizeable amount of data that must be trans-ferred off platform for comparison against a golden model. In this work we propose a sequence-by-sequence (SBS) check-ing approach that is efficient and practical for acceleration plat-forms. Our SBS checking solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found experimentally that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by>90%. 1