An Energy-Efficient Ternary Interconnection Link for Asynchronous Systems

Abstract- We introduce a new ternary link including a binary- The most common implementation of this protocol is the dual-rail to-ternary encoder and a ternary-to-binary decoder in voltage-mode signaling scheme with return to zero. This consists in doubling the multiple-valued logic (MVL). This link improves the transistor count number of wires to code the information as it is described by Fig. compared to existing designs and it has no DC current path. The complete link was simulated with SPICE and a 0.13pim CMOS technology. It 2 An important disadvantage of this method is that the number of additionally shows interesting advantages on power consumption for wires is very high and it makes wire routing very difficult and also global interconnects compared to full-swing signaling binary systems (up time and power consuming. to 56.4 % less energy consumption). Its low propagation delay is also an Recent researches have focused on reducing the interconnect area advantage in the design of high-speed on-chip links for asynchronous as well as the pin requirements. One idea consists in increasing the systems.-data rate on a wire by having more than two logic states: this research I. INTRODUCTION field is called multiple-valued logic (MVL). This idea is also used to In modern CMOS technologies, interconnects represent a signifi- design high-speed inter-chip links using pulse-amplitude modulation cant part of the power consumption (up to 50%) [1] and of the chip (PAM) [6]. The voltage mode ternary equivalent of the dual-rail area. New constraints (such as costs or speed) on systems-on-chip encoding with return to zero is also shown on Fig. 2