Abstract. In this paper we describe ASH, an architectural framework for imple-menting Application-Specific Hardware. ASH is based on automatic hardware synthesis from high-level languages. The generated circuits use only localized computation structures; in consequence, we expect these circuits to be fast, to use little power and to scale well with program complexity. We present in detail CASH, a scalable compiler framework for ASH, which generates hardware from programs written in C. Our compiler exploits instruction level parallelism by using aggressive speculation and dynamic scheduling. Based on this compilation scheme, we evaluate the computational resources necessary for implementing complex integer-based programs, and we suggest arch...
The next decade of computing will be dominated by embedded systems, information appliances and appli...
Abstract. Various languages have been proposed to describe synchronous hardware at an abstract, yet ...
This paper explores a novel way to incorporate hardware-programmable resources into a processor micr...
reconfigurable computing, power-efficient computation This thesis presents a compilation framework f...
A hardware implementation can bring orders of magnitude improvements in performance and energy consu...
A hardware implementation can bring orders of magnitude improvements in performance and energy cons...
We explain how programs specified in a sequential programming language can be translated automatical...
The next decade of computing will be dominated by embedded systems, information appliances and appli...
A common approach to decreasing embedded application execution time is creating a homogeneous parall...
Today's cutting-edge applications, ranging from wearable devices and embedded medical sensors to hig...
. This paper reports recent work on the automatic design and implementation of microprocessors to su...
There is today an ever-increasing demand for more computational power coupled with a desire to minim...
This paper presents the hardware/software generation backend of a code generation framework. The bac...
Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a ...
This paper describes an automated approach to hardware design space exploration, through a collabora...
The next decade of computing will be dominated by embedded systems, information appliances and appli...
Abstract. Various languages have been proposed to describe synchronous hardware at an abstract, yet ...
This paper explores a novel way to incorporate hardware-programmable resources into a processor micr...
reconfigurable computing, power-efficient computation This thesis presents a compilation framework f...
A hardware implementation can bring orders of magnitude improvements in performance and energy consu...
A hardware implementation can bring orders of magnitude improvements in performance and energy cons...
We explain how programs specified in a sequential programming language can be translated automatical...
The next decade of computing will be dominated by embedded systems, information appliances and appli...
A common approach to decreasing embedded application execution time is creating a homogeneous parall...
Today's cutting-edge applications, ranging from wearable devices and embedded medical sensors to hig...
. This paper reports recent work on the automatic design and implementation of microprocessors to su...
There is today an ever-increasing demand for more computational power coupled with a desire to minim...
This paper presents the hardware/software generation backend of a code generation framework. The bac...
Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a ...
This paper describes an automated approach to hardware design space exploration, through a collabora...
The next decade of computing will be dominated by embedded systems, information appliances and appli...
Abstract. Various languages have been proposed to describe synchronous hardware at an abstract, yet ...
This paper explores a novel way to incorporate hardware-programmable resources into a processor micr...