A High-level Design and Implementation Platform for IP Prototyping on FPGA

Abstract — The purpose of this platform is to provide a design and implementation environment for prototyping both computational and controller functions, in a standard communication architecture, including an Atmel AVR micro-controller and a Wishbone bus protocol. This platform serves the goal of the fast implementation and test of a data-path or controller IP blocks in an FPGA. The purpose of the proposed design flow is to support a behavior design and implementation flow. The design flow consists of a scheduling and mapping tool and a number of free and commercial EDA tools. To provide for a ‘classroom ’ laboratory design envi-ronment, we have additionally designed a Wishbone slave IP interface, allowing for easy integration of VHDL blocks to be designed by the MSc students. After scheduling and mapping the operations of a ‘student function ’ in time and on resources, the EDA program generates the standardized interface as VHDL entities and component statements. The usage of this interface has the additional advantage of making avail-able to the designer VHDL test-bench template files to be used in a simulation environment. Finally, the design can be tested on a Xilinx FPGA development board