ufar Keywords: Chip Multiprocessor Network-on-Chip

ltip icat al a l be ences among messages belonging to different applications. The first model handles most interferences among messages with a virtual-channels (VCs) implementation reducing both execution time and net-ultipro e sam requirement. Networks on chip (NoCs) [3] are required to meet the challenges imposed by the most advanced chip technologies to become part of future CMP systems. Traditionally, the CMP platform is well designed for a single parallel application. In that case there are no cache interferences or network collisions. However, most applications do not present applications generating high cache miss rates. Then, minimizing network latency should be a priority on interconnects for such systems. Therefore, in this scenario where several applications run simultaneously on a CMP, all the resources in the CMP are shared by the applications, and if resources usage is not efficient, perfor-mance of any individual application can be seriously affected. Note that in those cases we do not want to improve the performance of individual applications, but to keep the individual application performance in the same values that when they are run alone, ⇑ Corresponding author