Energy and Design Cost Efficiency for Streaming Applications on Systems-on-Chip

iii With the increasing capacity of today’s integrated circuits, a number of heterogeneous system-on-chip (SoC) architectures in embedded systems have been proposed. In order to achieve energy and design cost efficient streaming applications on these systems, new design space exploration frameworks and performance analysis approaches are required. This thesis considers three state-of-the-art SoCs architectures, i.e., the multi-processor SoCs (MPSoCs) with network-on-chip (NoC) communication, the hybrid CPU/FPGA SoCs, and the run-time reconfigurable (RTR) FPGAs. The main topic of the au-thor’s research is to model and capture the application scheduling, archi-tecture customization, and buffer dimensioning problems, according to the real-time requirement. While these problems are NP-complete, both heuris-tic algorithms and the constraint solver are exploited in solutions finding. On NoC communication based MPSoCs, an approach to optimize th