An efficient quality-aware memory controller for multimedia platform SOC

allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory con-troller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory inter-face socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Exper-imental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%–65 % and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control. Index Terms—Memory controller, multimedia application, quality-aware scheduler (QAS). I