1Modeling Lifetime Reliability of Processor Cores

Rapid advances in VLSI technology have led to scaling of Modern CMOS Technologies. With feature size shrinking to smaller dimensions, the voltage scaling is not proportional. As a result, there is increase in power and current density, resulting in localized heating of some regions of the circuit. This leads to temperature variations across the chip, causing reliability issues and may ultimately trigger entire chip failure. Hence, increased temperatures across a chip have been identified as one of the major causes of chip failure. The challenge in recent times has been to build robust systems with built-in resilience to factors contributing to reliability degradation with minimal increase in cost and minimal impact on performance. With this as the primary motive, our project aims at modeling the lifetime reliability of the OpenRISC1200 (also abbreviated as OR1200) processor core [7] under specific workload conditions. We achieve this goal by performing power analysis and thermal profiling on each block of OR1200 processor core and then calculating Mean Time to Failure for each of these blocks (MTTF). This report presents the project objectives; previous work and motivation for the project; OR1200 simulation environment; switching activity dump obtained from OR1200 post synthesis simulation, Power analysis and Thermal profiling results for each block of OR1200