Scratchpad memory: design alternative for cache on-chip memory in embedded systems

In this paper we address the problem of on-chip mem-ory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using the trace results of the simulator. The tar-get processor chosen for evaluation was AT91M40400. The results clearly establish scratehpad memory as a low power alternative in most situations with an average energy re-duction of J0%. Further the average area-time reduction for the seratchpad memory was 46 % of the cache memory. 1 1. In t roduct ion The salient feature of portable devices is light weight and low power consumption. Applications n multimedia, video processing, speech processing, DSP applications and wire-less communication require efficient memory design since on chip memory- occupies more than 50 % of the total chip area [1]. This will typically reduce the energy consumption of the memory unit, because l ss area implies reduction in the total switched capacitance. On chip caches using static RAM consume power in the range of 25 % to,~5% of the total chip power [2]. Recently, interest has been fo-cussed on having on chip scratch pad memory to reduce the power and improve performance. On the other hand, they can replace caches only if they axe supported by an effec-tive compiler. Current embedded processors particularly in the area of multimedia applications and graphic ontrollers ZThis project is supported under DST-DAAD grant