An EÆcient Compiler Technique for Code Size Reduction using Reduced Bit-width ISAs

F or many embedded applications, program code size is a critic al design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor ar chite ctur es support a normal (usually 32 bit) Instruction Set, and a narr ow, space-eÆcient (usually 16 bit) Instruction Set with a limited set of op-codes and access to a limited set of r egisters.This fea-ture, however, requir escompilers that can reduc ecode size by compiling for both Instruction Sets. Existing compiler techniques operate at the function-level gran-ularity and are unable to make the trade-o betwe en in-creased register pr essure (resulting in more spills) and decreased code size. We present a protability based compiler heuristic that operates at the instruction-level granularity and is able to eectively take advantage of both Instruction Sets. We also demonstrate improved code size r eduction, for the MIPS 32/16 bit ISA, using our technique. Our appr oachmore than doubles the code size r eduction achieved by existing compilers.