Variational Capacitance Extraction of On-Chip Interconnects Based on Continuous Surface Model

In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increasing the number of variables. Based on it, efficient techniques are presented for chip-level capacitance extraction considering the window technique. The sparse-grid-based Hermite polynomial chaos combined with a novel weighted principle factor analysis is employed for intra-window extraction. Then, the inter-window capacitance covariance is calculated through matrix pseudo inverse. Numerical results validate the accuracy and efficiency of the proposed method, which is more than 50 times faster than the Monte-Carlo simulation with 10000 samples