A design framework to efficiently explore energy-delay tradeofss

Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architec-tural tradeoffs accounting for both energy and performance constraints. In this paper, we propose a system-level de-sign methodology for the efficient exploration of the mem-ory architecture from the energy-delay combined perspec-tive. The aim is to find a sub-optimal configuration of the memory hierarchy without performing the exhaustive analy-sis of the parameters space. The target system architecture includes the processor, separated instruction and data level-one caches, the main memory, and the system buses. The methodology is based on the sensitivity analysis of the op-timization function with respect to the tuning parameters of the cache architecture (mainly cache size, block size and associativity). The effectiveness of the proposed method-ology has been demonstrated through the design space ex-ploration of a real-world example: a MicroSPARC2-based system running the Mediabench suite. Experimental results have shown an optimization speedup of 329 times with re-spect to the full search, while the near-optimal system-level configuration is characterized by a distance from the optimal full search configuration in the band of 10%. 1