Add to ORKGAbstract { In this paper we examine the prob-lem of reducing the power consumption of a technol-ogy mapped circuit under timing constraints. Consider a cell library that contains multiple implementations (cells) of the same Boolean function. We rst present an exact algorithm for the problem when a complete library is given { in a complete library, \all " implemen-tations of each cell are present. We then propose an ecient algorithm for the problem if the provided li-brary is not complete.
In Standard cell library based design methodology, maintaining multiple driving strengths for each g...
Abstract—Today, many chips are designed with predefined discrete cell libraries. In this paper we pr...
Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing, that is...
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more c...
With increasing time-to-market pressure and shortening semi-conductor product cycles, more and more ...
[[abstract]]This paper describes methods for reducing power consumption. We propose using gate sizin...
This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a sta...
Abstract—Gate sizing has a significant impact on the de-lay, power dissipation, and area of the fina...
This paper examines the problem of minimizing the area of a synchronous sequential circuit for a giv...
With the remarkable growth of portable application and the increasing frequency and integration dens...
[[abstract]]In this paper, technology mapping algorithms for minimizing power consumption in FPGA de...
textIn today's world, it is becoming increasingly important to be able to design high performance in...
We propose a new power consumption model which accounts for the power consumption at the internal no...
Traditionally, three metrics have been used to evaluate the quality of logic circuits -- size, speed...
Cell libraries are collections of logic cores (cells) used to construct larger chip designs; hence, ...
In Standard cell library based design methodology, maintaining multiple driving strengths for each g...
Abstract—Today, many chips are designed with predefined discrete cell libraries. In this paper we pr...
Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing, that is...
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more c...
With increasing time-to-market pressure and shortening semi-conductor product cycles, more and more ...
[[abstract]]This paper describes methods for reducing power consumption. We propose using gate sizin...
This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a sta...
Abstract—Gate sizing has a significant impact on the de-lay, power dissipation, and area of the fina...
This paper examines the problem of minimizing the area of a synchronous sequential circuit for a giv...
With the remarkable growth of portable application and the increasing frequency and integration dens...
[[abstract]]In this paper, technology mapping algorithms for minimizing power consumption in FPGA de...
textIn today's world, it is becoming increasingly important to be able to design high performance in...
We propose a new power consumption model which accounts for the power consumption at the internal no...
Traditionally, three metrics have been used to evaluate the quality of logic circuits -- size, speed...
Cell libraries are collections of logic cores (cells) used to construct larger chip designs; hence, ...
In Standard cell library based design methodology, maintaining multiple driving strengths for each g...
Abstract—Today, many chips are designed with predefined discrete cell libraries. In this paper we pr...
Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing, that is...