As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell components. This work begins by demonstrating that conventional Half-PerimeterWire Le-ngth (HPWL)-driven placers under-perform in terms of regularity and Steiner Wire Length (StWL) for such hybrid designs, and the quality gap between manual placement and automatic placers is more pronounced as the designs become more datapath-oriented. Then, a new unified placement flow that simultaneously handles random logic and datapath standard cells is proposed that signifi-cantly improves the placement quality of the datapath while lever-aging the speed of modern state-of-the-ar...
As the technology advances, millions of transistors can be integrated on a small chip area. The proc...
The use of white space in fixed-die standard-cell placement is an ef-fective way to improve routabil...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
In this paper we study the correlation between wirelength and routability for standard-cell placemen...
In this paper we study the correlation between wirelength and routabil-ity for standard-cell placeme...
Regular structures, like datapath, are important components of integrated circuits. Datapath logic i...
Electronic Design Automation (EDA) tools have revolutionised the way digital integrated circuits are...
We show how to optimize Steiner-tree Wirelength (StWL) in global and detail placement without a sign...
Abstract—Wirelength is one of the most important metrics in placement problem. Minimizing wirelength...
Abstract — Automated cell placement is a critical problem in VLSI physical design. New analytical pl...
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size place...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
The placement of cells in Integrated Circuit Design Automation has a major influence on overall desi...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
As the field programmable gate array (FPGA) industry grows device capacity with Moore's law and exp...
As the technology advances, millions of transistors can be integrated on a small chip area. The proc...
The use of white space in fixed-die standard-cell placement is an ef-fective way to improve routabil...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
In this paper we study the correlation between wirelength and routability for standard-cell placemen...
In this paper we study the correlation between wirelength and routabil-ity for standard-cell placeme...
Regular structures, like datapath, are important components of integrated circuits. Datapath logic i...
Electronic Design Automation (EDA) tools have revolutionised the way digital integrated circuits are...
We show how to optimize Steiner-tree Wirelength (StWL) in global and detail placement without a sign...
Abstract—Wirelength is one of the most important metrics in placement problem. Minimizing wirelength...
Abstract — Automated cell placement is a critical problem in VLSI physical design. New analytical pl...
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size place...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
The placement of cells in Integrated Circuit Design Automation has a major influence on overall desi...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
As the field programmable gate array (FPGA) industry grows device capacity with Moore's law and exp...
As the technology advances, millions of transistors can be integrated on a small chip area. The proc...
The use of white space in fixed-die standard-cell placement is an ef-fective way to improve routabil...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...