Published In Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Future deep sub-micron technologies will be charac-terized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolflows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algo-rithms, based on timing interval analysis, for improving ex-isting asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal al-gorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding bet-ter average-case latencies than their synchronous counter-parts.