A Dynamically Reconfigurable Adaptive Viterbi Decoder

The use of error-correcting codes has proven to be an effec-tive way to overcome data corruption in digital communi-cation channels. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy. In this paper, we describe the analysis and implementation of a reduced-complexity de-code approach, the adaptive Viterbi algorithm (AVA). Our AVA design is implemented in reconfigurable hardware to take full advantage of algorithm parallelism and specializa-tion. Run-time dynamic reconfiguration is used in response to changing channel noise conditions to achieve improved decoder performance. Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4036-based PCI board. An overall decode performance improvement of 7.5X for AVA has been achieved versus algorithm imple-mentation on a Celeron-processor based system. The use of dynamic reconfiguration leads to a 20 % performance im-provement over a static implementation with no loss of de-code accuracy