Abstract—Transactional memory is currently a hot research topic, having attracted the focus of both academic researchers and development groups at companies. Indeed, the concept of transactional memory has recently attracted much interest for multicore systems as it eases programming and avoids the problems of lock-based methods. However, up to now, the scheduling of real-time transactions within software transactional memories has not been studied. To address this issue, we present in this paper a real-time software transactional memory, namely RT-STM. We focus on the scheduling of concurrent soft real-time transactions. In particular, we explore a new heuristic for conflict resolution that reduces the number of deadline violations when sc...
We consider multiprocessor distributed real-time systems where concurrency control is managed using ...
International audienceTransactional memory has attracted much interest for multicore systems as it e...
Software Transactional Memory (STM) can be defined as a generic nonblocking synchronization construc...
9 pagesInternational audienceTransactional memory is currently a hot research topic, having attracte...
Lock-based concurrency control suffers from programmability, scalability, and composability challeng...
The foreseen evolution of chip architectures to higher number of, heterogeneous, cores, with non-un...
We consider software transactional memory (STM) concurrency control for embedded multicore real-time...
Abstract—Software Transactional Memory (STM) is an op-timistic concurrency control mechanism that si...
8 pagesInternational audienceWhile real-time applications are becoming more and more concurrent and ...
Software transactional memory (STM) is an optimistic concurrency control mechanism that simplifies p...
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent ca...
Directeur de thèse: Patrick Valduriez, co-encadrante: Audrey QueudetWith the advent of multicore sys...
There has been considerable recent interest in the support of transactional memory (TM) in both har...
In the last few years, Transactional Memories (TMs) have been shown to be a parallel programming mod...
Transactional Memory (TM) is a practical programming paradigm for developing concurrent applications...
We consider multiprocessor distributed real-time systems where concurrency control is managed using ...
International audienceTransactional memory has attracted much interest for multicore systems as it e...
Software Transactional Memory (STM) can be defined as a generic nonblocking synchronization construc...
9 pagesInternational audienceTransactional memory is currently a hot research topic, having attracte...
Lock-based concurrency control suffers from programmability, scalability, and composability challeng...
The foreseen evolution of chip architectures to higher number of, heterogeneous, cores, with non-un...
We consider software transactional memory (STM) concurrency control for embedded multicore real-time...
Abstract—Software Transactional Memory (STM) is an op-timistic concurrency control mechanism that si...
8 pagesInternational audienceWhile real-time applications are becoming more and more concurrent and ...
Software transactional memory (STM) is an optimistic concurrency control mechanism that simplifies p...
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent ca...
Directeur de thèse: Patrick Valduriez, co-encadrante: Audrey QueudetWith the advent of multicore sys...
There has been considerable recent interest in the support of transactional memory (TM) in both har...
In the last few years, Transactional Memories (TMs) have been shown to be a parallel programming mod...
Transactional Memory (TM) is a practical programming paradigm for developing concurrent applications...
We consider multiprocessor distributed real-time systems where concurrency control is managed using ...
International audienceTransactional memory has attracted much interest for multicore systems as it e...
Software Transactional Memory (STM) can be defined as a generic nonblocking synchronization construc...