Design techniques of FPGA based random number generator

Random numbers are required in a wide variety of applications. As digital systems become faster and denser, it is feasible, and frequently necessary, to implement ra dom number generators directly in hardware. In this paper, we describe techniques suitable for hardware implementation, including one-bit true random number generator, one-bit LFSR (Linear Feedback Shift Register) generator, multiple-bit LFSR generator, multiple-bit leap-forward LFSR generator, and multiple-bit lagged Fibonnaci generator. We also discuss the benefit of each technique and its circuit complexity, particularly for implementation utilizing FPGA (Field Programmable Gate Array) devices. I