J Sign Process Syst DOI 10.1007/s11265-010-0478-5 Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

Abstract This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a par-allelism level classification and characterization. From this design space exploration, an innovative TPC de-coder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with exist-ing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)2 product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders an