Comparing cache architectures and coherency protocols on x86-64 multicore smp systems

Across a broad range of applications, multicore technol-ogy is the most important factor that drives today’s mi-croprocessor performance improvements. Closely coupled is a growing complexity of the memory subsystems with sev-eral cache levels that need to be exploited efficiently to gain optimal application performance. Many important imple-mentation details of these memory subsystems are undocu-mented. We therefore present a set of sophisticated bench-marks for latency and bandwidth measurements to arbitrary locations in the memory subsystem. We consider the co-herency state of cache lines to analyze the cache coherency protocols and their performance impact. The potential of our approach is demonstrated with an in-depth compari-son of ccNUMA multiprocessor systems with AMD (Shang-hai) and Intel (Nehalem-EP) quad-core x86-64 processors that both feature integrated memory controllers and coher-ent point-to-point interconnects. Using our benchmarks we present fundamental memory performance data and archi-tectural properties of both processors. Our comparison re-veals in detail how the microarchitectural differences tremen-dously affect the performance of the memory subsystem