Tolerating Operational Faults in Cluster-Based FPGAs

In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault toler-ance. While these systems frequently contain hardware redundan-cy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full func-tionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance gen-erally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults. Our preferred approach to fault recovery takes advantage of device routing hierarchy in archi-tectural families such as Xilinx Virtex [2] and Altera Apex [3] to quickly swap unused logic and routing resources in place of faulty ones within logic clusters. These algorithms allow for straightfor-ward implementation within a local fault-tolerant system without the need to access a remote processing location. If initial recov-ery attempts through localized swapping fail, an incremental router based on the widely-used PathFinder maze routing algorithm [10] can be applied remotely in an attempt to form connections between newly-allocated logic and interconnect based on the history of the initial design route.