Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures

Abstract — The increasing wire delay constraints in deep sub-micron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL- inter-router, dual-function energy and area-efficient links capa-ble of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by control-ling the repeaters along the links to adaptively function as link buffers during congestion, thereby achieving nearly 30 % savings in overall network power and 35 % reduction in area with only a marginal 1 − 3 % drop in performance. In addition, aggres-sive speculative flow control further improves the performance of iDEAL. Moreover, the significant reduction in power consump-tion and area provides sufficient headroom for monitoring Neg-ative Bias Temperature Instability (NBTI) effects in order to im-prove circuit reliability at reduced feature sizes. I