FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems Sumanta

The Run-Time Reconfigurable (RTR) feature is highly de-sirable for flexible and fast self-contained systems. RTR can be achieved on some commercial FPGA platforms. We pro-pose an open solution, called FASE, that allows for fine-grain RTR, designed to be more intuitive than currently available solutions. The issues of initializing RTR soft IP-cores and a design flow to manage the dynamics of RTR are presented. In the context of secure embedded systems, there is a need for both flexibility and tamper-resistance. However, the robustness level for security constraints is difficult to get and to prove because of the proprietary hidden struc-tures. The FASE architecture addresses these issues. It makes it possible for any designer to implement custom and arbitrary dynamic strategies. We illustrate two case stud-ies: an implementation-level counter-measure against side-channel attacks and an efficient strategy to thwart fault in-jection attacks against cryptographic functions. 1