Communication Service and Dynamic Memory Management for hardware tasks executed on Dynamic and Partial Reconfigurable resources

Recent developments in the Dynamic and Partial Reconfigurable Computing requires the presence of Operating System (OS) services like scheduler, placer, reconfiguration manager etc to manage the run-time activities in the reconfigurable resource. In this thesis, we address the Inter-Task communication, which is one of the OS ser-vices required to manage run-time communication between dynam-ically configured hardware tasks. The scheduler may configure the hardware task in any available Partial Reconfigurable Regions. In order to provide high throughput, flexible and scalable Inter-Task Communication service between the hardware tasks configured dy-namically, we have developed a hardware Communication Service block to establish the communication between them. The system was implemented in Xilinx ML506 evaluation platform containing Virtex-5 FPGA. Performance and implementation cost of our hard-ware communication service design are presented and compared with the current state of art. Our solution is 60 × faster than OS4RS in establishing communication and provides 3 × more throughput than RECONOS. Moreover, as a proof of concept AES application was ported in the system and the results are compared with the equiva-lent software implementation