in A Flexible Design Flow for Software IP Binding in Commodity FPGA

Figure 1. SWIP binding to a platform comprised of HWIP and an FPGA. Our main contributions in this paper are as follows-• To propose a complete, end-to-end design flow to bind a SWIP to an FPGA utilizing a PUF. Platform 3Platform 2 To demonstrate a complete prototype implementation using our design flow to prove the validity of our idea. To our knowledge, this is the first work to demonstrate such an implementation. To develop necessary tools for the proposed design flow such as the Intellectual Property Encryptor (IPE) and an obfuscated ROM. Platform 1 SWIP binding can be achieved using costly mechanisms such as secure ROM or flash memory to store FPGA specific cryptographic keys. This is not only expensive but also vulnerable to attack [8, 9]. In this work, we instead utilize the ability of a PUF to generate a FPGA-unique secret volatile key to achieve SWIP binding. functions correctly when a valid HWIP and a valid FPGA are present, such as with platform 2. Platform 3 fails because the FPGA device is not valid, while platform 1 fails because the HWIP is not valid. The identity of a design is thus formed by the combination of an FPGA and a HWIP. In this work, we propose an end-to-end design flow for binding a SWIP to a commodity FPGA. This paper proposes a novel design flow for protecting SWIP by binding it to a specific FPGA platform. We accomplish this by leveraging the qualities of a Physical Unclonable Function (PUF) and a tight integration of hardware and software security features. A prototype implementation demonstrates our design flow to successfully protect a SWIP by encryption using a 128 bit FPGA-unique key extracted from a PUF. I