A Retargatable, Ultra-fast Instruction Set Simulator

In this paper, we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such uti-lization is achieved by defining a low level code generation inter-face specialized for ISA simulation, rather than the traditional ap-proaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 102 millions of simu-lated instructions per second (MIPS). This result is only 1:1 2:5 times slower than the native execution on the host machine, the fastest to the best of our knowledge. Furthermore, the code gen-eration interface is organized to implement a RISC like virtual machine, which makes our tool easily retargetable to many host platforms.