The demand for compute cycles needed by embedded systems is rapidly increasing. Due to the limitations of single-core processors, a move towards multi-core architectures is unavoidable. In this paper, we introduce the XGRID embedded many-core system-on-chip architecture. XGRID makes use of a novel, FPGA-like, programmable interconnect infrastructure, offering scalability and deterministic communication using hardware supported message passing among cores. We have developed a simulation framework for the XGRID architecture, which provides system performance information. Our experiments with XGRID are very encouraging. A number of parallel benchmarks are evaluated on the XGRID processor using the application mapping technique described in thi...
In this work, we propose a configurable many-core overlay for high-performance embedded computing. T...
In single processor architectures, computationally-intensive functions are typically accelerated usi...
International audienceEstimating the potential performance of parallel applicationson the yet-to-be-...
Abstract—The demand for compute cycles needed by embedded systems is rapidly increasing. In this pap...
Single processor architectures are unable to provide the required performance of high performance em...
Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the appl...
International audienceMassively parallel architectures are proposed as a promising solution to speed...
Applications running on custom architectures with hundreds of specialized processing elements (PEs) ...
Due to the advancements of VLSI technologies, we can put more cores on a chip, resulting in the emer...
To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose compu...
To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose compu...
Data-Flow Threads (DF-Threads) is a new execution model that permits to seamlessly distribute the wo...
Many-core hardware is targeted specifically at obtaining high performance, but reaching high perform...
Improving the performance of future computing systems will be based upon the ability of increasing t...
Many-core hardware is targeted specifically at obtaining high performance, but reaching high perform...
In this work, we propose a configurable many-core overlay for high-performance embedded computing. T...
In single processor architectures, computationally-intensive functions are typically accelerated usi...
International audienceEstimating the potential performance of parallel applicationson the yet-to-be-...
Abstract—The demand for compute cycles needed by embedded systems is rapidly increasing. In this pap...
Single processor architectures are unable to provide the required performance of high performance em...
Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the appl...
International audienceMassively parallel architectures are proposed as a promising solution to speed...
Applications running on custom architectures with hundreds of specialized processing elements (PEs) ...
Due to the advancements of VLSI technologies, we can put more cores on a chip, resulting in the emer...
To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose compu...
To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose compu...
Data-Flow Threads (DF-Threads) is a new execution model that permits to seamlessly distribute the wo...
Many-core hardware is targeted specifically at obtaining high performance, but reaching high perform...
Improving the performance of future computing systems will be based upon the ability of increasing t...
Many-core hardware is targeted specifically at obtaining high performance, but reaching high perform...
In this work, we propose a configurable many-core overlay for high-performance embedded computing. T...
In single processor architectures, computationally-intensive functions are typically accelerated usi...
International audienceEstimating the potential performance of parallel applicationson the yet-to-be-...