Distributed TSV topology for 3-D power-supply networks

Abstract—3-D integration has the potential to increase perfor-mance and decrease energy consumption. However, there aremany unsolved issues in the design of these systems. In this workwe study the design of 3-D power supply networks and demonstrate a tech-nique specific to 3-D systems that improves IR-drop and dynamic noise over a straightforward extension of traditional design tech-niques. Previous work in 3-D power delivery network design has simply extended 2-D techniques by treating through-silicon vias (TSVs) as extensions of the C4 bumps. By exploiting the smaller size and much higher interconnect density possible with TSVs we demonstrate significant reduction of nearly 50 % in the IR-drop and 42 % in the dynamic noise of our large-scale 3-D design. Sim-ulations also show that a 3-tier stack with the distributed TSV topology actually lowers IR-drop by 21 % and dynamic noise by 32 % over a non-3-D system with less power dissipation. We an-alyze the power distribution network of an envisioned 1000-core processor with 30 stacked dies and show scaling trends related to both increased stacking and power distribution TSVs. Finally, we examine several techniques for minimizing IR-drop and dynamic noise and their effects on our large-scale 3-D system. Index Terms—3-D, inductive noise, power supply network, through-silicon via (TSV). I