Wilhelm-Schickard-Institut fUr Informatik

Image generation for raster displays proceeds in two main steps: geometry pro cessing and pixel processing. The snbsystem performing the pixel processing is called display processor. In the paper a model for the displa.y processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an in equation being fundamental for all display processor architectures. On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, a.rchitecture and performance. The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System. Investigation of existing display processor architectures on the basis of the devel oped taxonomy revealed a potential new architecture. This architecture partitions the image generation process ill image space and employs a. tree topology. eR Categories and Subject Descriptors