Cluster-based Detection of SEU-caused Errors in LUTs of

Abstract — This paper proposes a cluster-based parity-checking technique that can detect 100 % of all Single Event Up-set (SEU) faults in the LUTs of SRAM-based FPGAs. The pa-per describes two different Configurable Logic Block (CLB) ar-chitectures that could be used to implement the proposed SEU detection technique. Of the two, the first architecture can per-form at-speed testing of the LUTs without interrupting the nor-mal functioning of the FPGA. The second one works by switching the CLBs from normal-mode to testing-mode and vice-versa. The LUTs are tested in the testing-mode. The switching frequency can be externally programmed and hence varied depending on the rate of SEU occurrences. Both the proposed architectures were compared with the Xilinx Virtex and Virtex Pro architec-ture. The proposed architectures require only (when compared with Virtex) and (when compared with Virtex Pro) additional SRAM configuration bits per LUT. This is extremely low when compared to the additional SRAM configuration bits required by CLB architectures used to implement standard DWC tech-niques for detecting SEUs in LUTs. The area requirements of both the proposed architectures are also significantly less than the area requirements of DWC techniques. The proposed detection technique requires only clock cycles of the Xilinx Virtex inter-nal clock to detect the effect of an SEU in any LUT of the FPGA. I