Abstract—To study the substrate effect on inductor perfor-mance, several types of spiral inductors were fabricated on porous silicon (PS), p and p+ silicon substrate.-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher-factor and resonant frequency ( ) result from the reduced shunt conduc-tance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bu...
[[abstract]]The impact of two different types of floating patterns on spiral inductors was investiga...
The quality factor (Q) of two inductors for 5-60 GHz applications fabricated in an industrial back-e...
In this paper, a post-CMOS selective grown porous silicon (SGPS) technique is proposed to achieve hi...
International audienceTo study the effect of various n-type substrates on high-frequency inductor pe...
International audienceTo study the influence of localized porous silicon regions on radiofrequency p...
A new method to grow porous silicon substrate from the back-end of silicon substrate is presented. H...
The substrate effects on the performance of metal-insulator-metal (MIM) capacitors and spiral induct...
Inductor properties were studied using three different silicon-on-insulator (SOI) substrates: two fu...
Nowadays, as the demand for wireless communication continues to expand, the need for high quality (Q...
This paper describes a physical model for spiral inductors on silicon which is suitable for circuit ...
This paper presents a novel on-chip inductor with a patterned ground shield inserted between the spi...
This paper presents a novel technique to improve the quality factor (Q-factor) of a standard inducto...
A backside growth technique of thick porous silicon layers for the on-chip RF integrated inductor is...
This paper reports a new category of high-Q integrated inductor which is realized using post-CMOS se...
This paper reports on the fabrication and characterization of high quality factor (Q) copper (Cu) in...
[[abstract]]The impact of two different types of floating patterns on spiral inductors was investiga...
The quality factor (Q) of two inductors for 5-60 GHz applications fabricated in an industrial back-e...
In this paper, a post-CMOS selective grown porous silicon (SGPS) technique is proposed to achieve hi...
International audienceTo study the effect of various n-type substrates on high-frequency inductor pe...
International audienceTo study the influence of localized porous silicon regions on radiofrequency p...
A new method to grow porous silicon substrate from the back-end of silicon substrate is presented. H...
The substrate effects on the performance of metal-insulator-metal (MIM) capacitors and spiral induct...
Inductor properties were studied using three different silicon-on-insulator (SOI) substrates: two fu...
Nowadays, as the demand for wireless communication continues to expand, the need for high quality (Q...
This paper describes a physical model for spiral inductors on silicon which is suitable for circuit ...
This paper presents a novel on-chip inductor with a patterned ground shield inserted between the spi...
This paper presents a novel technique to improve the quality factor (Q-factor) of a standard inducto...
A backside growth technique of thick porous silicon layers for the on-chip RF integrated inductor is...
This paper reports a new category of high-Q integrated inductor which is realized using post-CMOS se...
This paper reports on the fabrication and characterization of high quality factor (Q) copper (Cu) in...
[[abstract]]The impact of two different types of floating patterns on spiral inductors was investiga...
The quality factor (Q) of two inductors for 5-60 GHz applications fabricated in an industrial back-e...
In this paper, a post-CMOS selective grown porous silicon (SGPS) technique is proposed to achieve hi...