A Systembased Performance Evaluation Framework for Dynamically Reconfigurable SoC

To cope with increasing demands for higher computational power and flexibility, dynamically reconfigurable logic has started to play an important role in Systems-on-Chip (SoC). However, it is difficult to analyze the performance impact of including such devices into a design, when using traditional design methods and tools. In this work, we present an easy-to-use system-level framework, which is able to perform rapid explorations of different reconfiguration alternatives and to detect system performance bottlenecks. This framework is based on SystemC, which is supported by most EDA tools