An Architecture of a Dataflow Single Chip Processor

A highly parallel (more than a thousand) datapoW machine EM-4 is now under development. The EM-4 &sign principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines. Constructing the EM-4, it is essential to fabricate a processing element (PE) on a sin-gle chip for reducing operation speed, system size, design complexhy and cost. In the EM-4. the PE. called EMC-R, has been specially designed using a 50,OOOgate gate array chip. This paper focuses on an architecture of the EMC-R. The distinctive features of it are: a strongly connected arc datafiow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular pipeline and a register-based advanced control pipeline. These features are intensively examined, and the instruction set architecture and the conftguration architecture which exploit them are &scribed. 1