Improved senseamplifier-based flip-flop: Design and measurements

Abstract—Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF’s is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and im-proves driving capability. The performance of this flip-flop is veri-fied by measurements on a test chip implemented in 0.18 m effec-tive channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Mea-surement techniques employed in this work as well as the measure-ment set-up are discussed in this paper. Index Terms—CMOS digital integrated circuits, clocking, flip-flops, sense-amplifier. I