This paper evaluates fault-tolerant behavior of an NoC router through simulation-based method. A structural-level VHDL environment has been employed to estimate fault injector signal’s (FIS) effects. Different fault models such as dead clause, stuck-then, micro-operation, crosstalk, and SEU have been injected to evaluate the transient faults ’ effects. According to the results, up to 48 % of the injected faults cause system failure and also about 51 % are overwritten before turning into errors. Less than 1 % of injected faults treat as latent errors. The average of fault latency has been investigated as 194ns. Almost 70%, 31%, and 35 % of injected faults are overwritten in buffer, routing unit, and switch components, respectively. Routing u...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
International audienceThe trend for processors consisting of more and more cores foreshadows chips c...
As CMOS technology scales to the nanometer range, designers have to deal with a growing number and v...
the progression of shrinking technologies into processes below 100nm has increased the importance of...
Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication...
Abstract — We present a fast parallel simulator to evaluate the impact of different error control me...
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacin...
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of proces...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
AbstractNetwork-on-Chip has become a hot spot in the field of complex System-on-Chip for its effecti...
In this work, we propose a fault-tolerant framework for Network on Chips (NoC) to achieve maximum pe...
Due to the character of the original source materials and the nature of batch digitization, quality ...
International audienceThe probability of transient faults increases with the evolution of technologi...
ISBN: 0769507190Analyzing at an early stage of the design the potential faulty behaviors of a circui...
Fault tolerant circuits are currently required in several major application sectors. Besides and in ...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
International audienceThe trend for processors consisting of more and more cores foreshadows chips c...
As CMOS technology scales to the nanometer range, designers have to deal with a growing number and v...
the progression of shrinking technologies into processes below 100nm has increased the importance of...
Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication...
Abstract — We present a fast parallel simulator to evaluate the impact of different error control me...
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacin...
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of proces...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
AbstractNetwork-on-Chip has become a hot spot in the field of complex System-on-Chip for its effecti...
In this work, we propose a fault-tolerant framework for Network on Chips (NoC) to achieve maximum pe...
Due to the character of the original source materials and the nature of batch digitization, quality ...
International audienceThe probability of transient faults increases with the evolution of technologi...
ISBN: 0769507190Analyzing at an early stage of the design the potential faulty behaviors of a circui...
Fault tolerant circuits are currently required in several major application sectors. Besides and in ...
International audienceThree-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative t...
International audienceThe trend for processors consisting of more and more cores foreshadows chips c...
As CMOS technology scales to the nanometer range, designers have to deal with a growing number and v...