A G-line-based Network for Fast and Efficient Barrier Synchronization in

Barrier synchronization in shared memory parallel ma-chines has been widely implemented through busy-waiting on shared variables. However, typical implementations of barrier synchronization tend to produce hot-spots in terms of memory and network contention, thus creating perfor-mance bottlenecks that become markedly more pronounced as the number of cores or processors increases. To over-come such limitations, we present a novel hardware-based barrier mechanism in the context of many-core CMPs. Our proposal is based on global interconnection lines (G-lines) and the S-CSMA technique, which have been recently used to enhance a flow control mechanism (EVC) in the context of networks-on-chip. Based on this technology, we have de-signed a simple and scalable G-line-based network that op-erates independently of the main data network, and that is aimed at carrying out barrier synchronizations efficiently. In the ideal case, our design takes only 4 cycles to perform a barrier synchronization once all cores or threads have ar-rived at the barrier. As a proof of concept, we examine the benefits of our proposal by comparing it with one of the best software approaches (a binary combining-tree barrier). To do so, we run several kernels and scientific applications on top of the Sim-PowerCMP performance simulator that mod-els a 32-core CMP with a 2D-mesh network configuration. Our proposal entails average reductions in terms of execu-tion time of 68 % and 21 % for kernels and scientific appli-cations, respectively. Additionally, network traffic is also lowered by 74 % and 18%, respectively.