The mesh Network-on-Chip (NoC) topology has its drawbacks in the communication latency scalability, and the concentration of the traffic in the center of the mesh. We propose a topology where a traditional wormhole-routed mesh network is augmented by a hierarchical ring intercon-nect for routing global traffic. In addition to the topology, the routing strategies have a large impact on system perfor-mance. We compare the performance of a deterministic and adaptive routing strategy when applied to our augmented topology. A SystemC modeling platform was used to com-pare the traditional wormhole–routed mesh with the aug-mented architecture. The proposed architecture reduces the average latencies incurred by global traffic, while the ap-plicatio...
Network on Chip is a scalable and flexible communication infrastructure for the design of core based...
As technology geometries have shrunk to the deep submicron regime, the communication delay and power...
<p>Energy consumption and design simplicity are paramount concerns in on-chip interconnects for chip...
This thesis investigates the properties of a hierarchical ring architecture, which is co...
Several models of deterministic routing have been proposed for wormhole-routed mesh networks while t...
As on-chip interconnection network scales to integrate more processing elements, physical limitation...
In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as...
As the technology is scaling, reducing wire delays is the major hurdle in increasing communication s...
A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore process...
This paper compares the performance of hierar-chical ring- and mesh-connected wormhole routed shared...
Multi and many-core applications are hungry for low on-chip network latency which is mainly determin...
A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore process...
2D-mesh and torus networks have often been proposed as the interconnection pattern for parallel comp...
A Hierarchical 3D-Mesh (H3DM) Network is a 2D-mesh network of multiple basic modules (BMs), in which...
Energy consumption of routers in commonly used mesh-based on-chip networks for chip multiprocessors ...
Network on Chip is a scalable and flexible communication infrastructure for the design of core based...
As technology geometries have shrunk to the deep submicron regime, the communication delay and power...
<p>Energy consumption and design simplicity are paramount concerns in on-chip interconnects for chip...
This thesis investigates the properties of a hierarchical ring architecture, which is co...
Several models of deterministic routing have been proposed for wormhole-routed mesh networks while t...
As on-chip interconnection network scales to integrate more processing elements, physical limitation...
In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as...
As the technology is scaling, reducing wire delays is the major hurdle in increasing communication s...
A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore process...
This paper compares the performance of hierar-chical ring- and mesh-connected wormhole routed shared...
Multi and many-core applications are hungry for low on-chip network latency which is mainly determin...
A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore process...
2D-mesh and torus networks have often been proposed as the interconnection pattern for parallel comp...
A Hierarchical 3D-Mesh (H3DM) Network is a 2D-mesh network of multiple basic modules (BMs), in which...
Energy consumption of routers in commonly used mesh-based on-chip networks for chip multiprocessors ...
Network on Chip is a scalable and flexible communication infrastructure for the design of core based...
As technology geometries have shrunk to the deep submicron regime, the communication delay and power...
<p>Energy consumption and design simplicity are paramount concerns in on-chip interconnects for chip...