A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in

Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feed-back equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ sig-naling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200 mVppd, one transmitter/receiver pair and one PLL consume 300 mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization. Index Terms—Adaptive equalizer, decision-feedback equalizer, feed-forward equalizer, serial link, transceiver. I