Structured ASIC Design: A New Design Paradigm beyond ASIC, FPGA AND SoC

Standard Cell ASICs are well known in the IC industry and have been successfully used over the past decade. During recent years there is a significant reduction of traditional ASIC design according to Gartner/Dataquest. (About 1/3rd the number of ASIC designs today compared to 3 or more years ago – See Figure 1)Trying to obey Moore’s law and the fact that mask costs passing $1M, design cycles expanding past a year and reliability issues arising from VDSM physical effects, it’s now require a massive production run to justify cell based ASIC. Yet, the demand for custom ASIC performance still remains for a wide variety of applications. In some cases, FPGA’s are successfully replacing ASIC’s despite their high unit costs, limited performance, high power consumption and power dissipation. Systems manufacturers may still achieve cost reduction in case the product is successful but this can be done in a later stage. The high cost of the development, masks, and tools can justify the production of very high-volume cell-based ASICs only. For mid-volume ASIC designs, the costs are simply becoming out of reach. The industry had to come with an effective and affordable solution. A different concept that will provide custom ASIC’s performance yet, with a short design cycle and low cost manufacturing. A new direction was taken, Structured ASICs. Structured ASICs offer a cost-effective solution for the mid-volume ASIC design with 75 % less development costs than cell-based ASICs and unit costs up-to 90 % less than complex FPGAs. (See Figure #2) In this article I will present a new design paradigm that has come of age, the structured ASIC