An efficient synchronization technique for multiprocessor systems on-chip

This paper explores optimization techniques of the syn-chronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future mobile systems. We suggest the architecture of the memory con-troller optimized to minimize synchronization overhead. The proposed solution is based on the idea of perform-ing synchronization operations which require the continu-ous polling of a shared variable, thus featuring large con-tention (e.g. spin locks), locally in the memory. We intro-duce a HW module, which augments the memory controller, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Exper-imental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For an 8-processor target architecture, we show that the proposed solution achieves up to 40 % performance im-provement and 25 % energy saving with respect to syn-chronization based on the caching of the synchronization variables and directory-based coherency protocol. Further-more, we prove the scalability of the proposed approach when the number of processors increases. 1